Soft repetition code combiner using channel state information

ABSTRACT

An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. 
     Another embodiment is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 12/478,673, filed Jun. 4, 2009 and claims the benefit of the provisional application, filed on Jun. 6, 2008, titled “Soft repetition code combiner using channel state information”, Ser. No. 61/059,706.

TECHNICAL FIELD

The presently disclosed embodiments are directed to the field of communication, and more specifically, to power line communication.

BACKGROUND

Power line communication (PLC) is a communication technology to carry data on electrical media (e.g., wires) that are used for electrical power transmission. Typically, electrical power is transmitted over high voltage transmission lines, distributed over medium voltage, and used inside commercial or residential buildings at lower voltages. Since powerline networks transmit data signals over the same electrical grid as that is used for carrying electrical power to commercial or residential buildings, electrical wires and sockets are used simultaneously for electricity and for data transmission, without causing disruption to either.

Broadband technologies provide high speed data transmission. However, currently it is problematic to apply broadband technologies in PLC. Some problems include the ability to efficiently decode signals in noisy channels, achieve time and frequency diversity, remove signal interference, maintain received signals at pre-determined levels, measure channel quality for high transmission rate, provide robustness to wideband and narrow band symbol synchronization.

SUMMARY

One disclosed feature of the embodiments is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision.

One disclosed feature of the embodiments is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments may best be understood by referring to the following description and accompanying drawings that are used to illustrate various embodiments. In the drawings.

FIG. 1 is a diagram illustrating a data frame structure used for data transmission and for the FCC, ARIB and CENELEC A bands according to one embodiment.

FIG. 2 is a diagram illustrating a symbol duration for data symbol according to one embodiment.

FIG. 3 is a diagram illustrating a data frame structure for data transmission for CENELECs B, C and BC according to one embodiment.

FIG. 4 is a diagram illustrating a symbol duration for data symbol for CENELC B and C according to one embodiment.

FIG. 5 is a diagram illustrating ACK signal for FCC, ARIB and CENELEC A according to one embodiment.

FIG. 6 is a diagram illustrating ACK signal for CENELEC B, C, and BC according to one embodiment.

FIG. 7 is a diagram illustrating a base-band transmitter according to one embodiment.

FIG. 8 is a diagram illustrating the FEC encoding unit according to one embodiment.

FIG. 9A is a diagram illustrating the data scrambler according to one embodiment.

FIG. 9B is a diagram illustrating the convolutional encoder according to one embodiment.

FIG. 10 is a diagram illustrating the modulator according to one embodiment.

FIG. 11A is a diagram illustrating the DBPSK modulator according to one embodiment.

FIG. 11B is a diagram illustrating the carrier index numbers according to one embodiment.

FIG. 11C is a diagram illustrating the input/output configuration according to one embodiment.

FIG. 12 is a diagram illustrating the PSD shaping module according to one embodiment.

FIG. 13A is a diagram illustrating a raised cosine function according to one embodiment.

FIG. 13B is a diagram illustrating a overlapping and add operation according to one embodiment.

FIG. 14 is a diagram illustrating a preamble signal according to one embodiment.

FIG. 15 is a diagram illustrating the pre-emphasis filter according to one embodiment.

FIG. 16 is a diagram illustrating the pre-emphasis filter according to one embodiment.

FIG. 17A is a diagram illustrating a data scaler on the transmitter data path according to one embodiment.

FIG. 17B is a diagram illustrating a P and M scaler on the transmitter data path according to one embodiment.

FIG. 17C is a diagram illustrating a scaler for frequency-domain P and M signals according to one embodiment.

FIG. 18 is a diagram illustrating a receiver according to one embodiment.

FIG. 19 is a diagram illustrating the demodulator according to one embodiment.

FIG. 20 is a diagram illustrating the FEC decoding unit according to one embodiment.

FIG. 21 is a diagram illustrating timings associated with events in the receiver according to one embodiment.

FIG. 22 is a diagram illustrating the DC blocker according to one embodiment.

FIG. 23 is a diagram illustrating the FFT according to one embodiment.

FIG. 24 is a diagram illustrating the DBPSK demodulator according to one embodiment.

FIG. 25 is a diagram illustrating the ROBO combiner/decoder according to one embodiment.

FIG. 26 is a diagram illustrating the RS decoder according to one embodiment.

FIG. 27 is a diagram illustrating the soft ROBO combiner/decoder according to one embodiment.

FIG. 28 is a diagram illustrating the channel state estimator using tone value according to one embodiment.

FIG. 29 is a diagram illustrating the four measurement regions over constellation plane according to one embodiment.

FIG. 30 is a diagram illustrating the tone value quantizer characteristics used to get soft values according to one embodiment.

FIG. 31 is a diagram illustrating the ROBO combiner/decoder using averaging according to one embodiment.

FIG. 32 is a diagram illustrating the averager according to one embodiment.

FIG. 33 is a diagram illustrating the performance on AWGN channel according to one embodiment.

FIG. 34 is a diagram illustrating the frequency selective channel model used in simulations according to one embodiment.

FIG. 35 is a diagram illustrating the performance in frequency selective fading according to one embodiment.

DETAILED DESCRIPTION

One disclosed feature of the embodiments is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision.

One disclosed feature of the embodiments is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

One disclosed feature of the embodiments may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc. One embodiment may be described by a schematic drawing depicting a physical structure. It is understood that the schematic drawing illustrates the basic concept and may not be scaled or depict the structure in exact proportions.

One disclosed feature of the embodiments is the implementation of a data communication modem for Federal Communication Commission (FCC), Association of Radio Industries and Businesses (ARIB), and European Committee of electrotechnical standardization or Comité Européen de Normalisation Electrotecnique (CENELEC) bands over the power line medium. The system may include a highly integrated PHY (physical layer) and MAC (Media Access Control) digital transceiver and analog front end processing circuits. The system is based on Orthogonal Frequency Division Multiplexing (OFDM). OFDM has been chosen as the modulation technique because of its inherent adaptability in the presence of frequency selective channels, its resilience to jammer signals, and its robustness to impulsive noise.

The OFDM system may place N_(carrier) evenly spaced carriers into a specified frequency band such as from DC to 1.2 MHz. In one embodiment, N_(carrier)=128. In the following description, the value N_(carrier)=128 will be used for illustrative purposes. It is contemplated that N_(carrier) may be any suitable number. Depending on the band selection, number of carriers participating in transporting data varies. Every carrier may be modulated with Differential Binary Phase Shift Keying (DBPSK). The system may support two modes of operation namely Normal and ROBO (Robust OFDM). The ROBO modulation is robust in the sense that it may provide four times extra redundancy parity bits by mean of repetition code and therefore the system may reliably deliver data under severe channel conditions.

The system parameters include signal frequency bands, modulation schemes, sampling frequency and physical layer frame structure, etc. The system supports various CELENEC, FCC and ARIB bands. The frequency band associated with each standard is given in Table 1.

TABLE 1 FCC, ARIB and CENELEC Bands F Low F High (KHz) (KHz) FCC 10 480 ARIB 10 450 CELENEC A 9 95 CELENEC B 95 125 CELENEC C 125 140 CELENEC B, C 95 140

An OFDM with DBPSK modulation scheme per carrier may be selected. The OFDM modulation technique is very robust against channel fading, narrowband interference and spike noise. The DBPSK modulation for each carrier may make the receiver design significantly simple since no tracking circuitry is required at the receiver for coherently detecting the phase of each carrier. In DBPSK demodulator, the phases of carriers in adjacent symbol may be taken as the reference for detecting the phases of the carriers in the current symbol. The phases of corresponding carriers in adjacent OFDM symbols may be expected to be stationary since the channel and the clock frequency variations in time are very slow as compared to the duration of two adjacent symbols.

Assuming the maximum spectral content of the signal is 480 KHz, the sampling frequency at the transmitter and receiver may be selected to be 1.2 MHz that is about 240 KHz above the Nyquist rate to provide a sufficient margin for signal filtering in the transmitter (for PSD shaping to remove the signal images) and at the receiver (for band selection and signal enhancement).

The number of frequency bins (FFT points) may be any suitable number. In one embodiment, this number is selected to be N=256. This results in a frequency resolution for the OFDM carriers equal to 4.6875 KHz (Fs/N). Note that imperfection such as sampling clock frequency variation may cause Inter Carrier Interference (ICI). In practice, the ICI caused by a typical sampling frequency variation about 2% of frequency resolution is negligible. In other word, considering ±20 ppm sampling frequency in transmitter and receiver clocks, the drift of the carriers may be approximately equal to 48 Hz that is approximately 1.26% of the selected frequency resolution. Considering these selections, the number of usable carriers for each standard may be obtained as given in Table 2.

TABLE 2 Number of carriers for various bands Number of Carriers (Ncarr) First Carrier Last Carrier (KHz) (KHz) (KHz) FCC 100 14.063 478.125 ARIB 93 14.0625 445.3125 CELENEC A 19 9.375 93.75 CELENEC B 6 98.4375 121.875 CELENEC C 3 126.5625 135.9375 CELENEC B, C 9 98.4375 135.9375

The system may work in two different modes namely Normal and ROBO modes. In Normal mode, the FEC may include a Reed Solomon encoder and a convolutional encoder. The system may also support Reed Solomon code with parity of 8 and 16 Bytes.

In ROBO mode (robust modulation scheme) the FEC may include Reed Solomon and convolutional encoders followed by a Repetition Code (RC). The RC code may repeat each bit four times making system more robust to channel impairments. This of course may reduce the throughput by a factor of 4. The FEC parameters for RS parity of 8 may be given in Table 3.

TABLE 3 FEC Parameters Normal Mode ROBO Mode FCC ½ convolutional Code + ½ convolutional Code + Reed Solomon (241/249) Reed Solomon (53/61) + RC (4) ARIB ½ convolutional Code + ½ convolutional Code + Reed Solomon (223/231) Reed Solomon (49/57) + RC (4) CENELEC A ½ convolutional Code + ½ convolutional Code + Reed Solomon (181/189) Reed Solomon (38/46) + RC (4) CENELEC BC ½ convolutional Code + ½ convolutional Code + Reed Solomon (171/179) Reed Solomon (36/44) + RC (4) CENELEC B ½ convolutional Code + ½ convolutional Code + Reed Solomon (111/119) Reed Solomon (21/29) + RC (4) CENELEC C ½ convolutional Code + ½ convolutional Code + Reed Solomon (111/119) Reed Solomon (21/29) + RC (4)

The number of symbols in each PHY (Physical Layer) frame may be selected based on two parameters, the required data rate and the acceptable delay. Since high bandwidth standard (FCC, ARIB) may be utilized for some delay sensitive applications such as voice transmission, therefore the number of symbols in PHY frame may be selected less that that of low bandwidth standard (CENELEC). The number of symbols and data rate associated with each band may be tabulated in Table 4. To calculate the data rate, the packets may be assumed to be continuously transmitted with no inter frame time gap.

TABLE 4 Data rate for various standards Data Data No. of Rate Rate symbols per (DBPSK) (ROBO) PHY Frame (kbps) (kbps) (Ns) FCC 170 37 40 ARIB 157 34 40 CELENEC A 37 7.7 160 CELENEC B 9.71 1.84 320 CELENEC C 4.9 0.93 640 CELENEC B, C 14.95 3.15 320

The data rate may be calculated based on the number of symbols per PHY frame (NS), number of carrier per symbol (Ncarr) and number of parity bits added by FEC blocks. As an example, consider the system in the FCC band working in ROBO mode. Total number of bits carried by the whole PHY frame may be equal to: Total_No_Bits=NS×Ncarr=40×100=4000 bits

The number of bits required at the input of ROBO encoder may be given by: No_Bits_ROBO=4000×ROBORate=4000×¼=1000 bits

Considering the fact that convolutional encoder may have a rate equal to ½ (CCRrate=½) and also consider adding CCZerotail=6 bits of zeros to terminate the states of the encoder to all zero states then the maximum number of symbols at the output of Reed Solomon encoder (MAXRSbytes) may be equal to: MAXRSbytes=floor((No_Bits_ROBO×CCRate×CCZeroTail)/8)=floor((1000×½−6)/8)=61

Symbols: Removing 8 symbols associated with the parity bits, we may obtain: DataLength=(61−ParityLength)×8=424 bits

These 424 bits may be carried within the duration of a PHY frame. The duration of a PHY frame may be calculated by the following formula: T_Frame=((NS×(N_CP+N−NO)+(Npre×N)))/Fs where Npre, N, NO and N_CP are the number of samples in the preamble, FFT length, the number of samples overlapped at each side of one symbol and the number of samples in the cyclic prefix, respectively. The Fs is the sampling frequency. Typical values for all these parameters for various frequency bands may be given in Table 5.

TABLE 5 Parameters for various frequency bands Number of FFT points N = 256 Number of overlapped samples NO = 8 Number of cyclic Prefix (CENELEC B and C) N_CP = 89 Number of cyclic Prefix (FCC, ARIB, CENELEC A) N_CP = 30 Sampling frequency Fs = 1.2 MHz

Replacing the above numbers in the equation, T-Frame (PHY frame duration) may be obtained as follows: T_Frame=(40×(256+22)+(9.5×256))/1200000=0.0112 sec.

Therefore the data rate may be calculated by: Data rate=424/0.0112˜37 kbps

Signal Types: There are 2 transmission commands to the physical layer as described below.

FIG. 1 is a diagram illustrating a data frame structure 100 used for data transmission and for the FCC, ARIB and CENELEC A bands according to one embodiment. The data frame 100 includes a preamble portion 110 and a data symbol portion 120.

The preamble 110 may include 8 identical P symbols and 1½ identical M symbols. Each symbol may be 256 samples and may be pre-stored in the transmitter and may be transmitted right before the data symbols. The symbols P may be used for AGC adaptation, symbol synchronization, channel estimation and initial phase reference estimation. For M symbols, two types of symbol may be used. One is the M1 in which all the carriers may be π phase shifted and the other one is M2 in which all the carriers may be π/2 phase shifted. M1 is used in ROBO mode and M2 may be used in Normal mode. At the receiver, the phase distance between symbol P and symbol M waveforms may be used for frame synchronization purpose. And the distance between the phases of two possible M symbols may be used to detect whether the PHY frame is sent in Normal mode or in ROBO mode.

FIG. 2 is a diagram illustrating a symbol duration for data symbol according to one embodiment. Each symbol may have 8 samples overlapped with adjacent symbols. The last 8 samples (tail) of preamble may also be overlapped with the 8 samples of the first data symbol (head) as shown in the FIG. 2. The overlap may be included to smooth the transition between symbols thus reducing the out of band spectral growth.

FIG. 3 is a diagram illustrating a data frame structure 300 for data transmission for CENELECs B, C and BC according to one embodiment. The data frame 300 includes a preamble portion 310 and a data symbol portion 320.

The preamble 310 for CENELECs B, C & BC bands may include for special symbols labeled as F1F2 symbols, followed by four identical P symbols and 1½ identical M symbols. For CENELEC C, each F1F2 symbol may include three sinewaves whose phases may switch by 180° after 256 samples. Hence, we generate 256 samples of each of the three tones and sum them together, then we add 180° phase shift to each of the three tones and generate another 257 samples, so that the total length of an F1F2 symbol may be 513 samples. For CENELECs B & BC, six tones may be used instead of three, but the length of the F1F2 symbols remains unchanged. The F1F2 symbols may be used for synchronization. Each preamble symbol may contain 513 samples. The reason that we have used a different technique for synchronization is that the allocated bandwidth in CENELECs C, B and BC may be too small, which makes the autocorrelation property of the P symbols not good enough for robust synchronization. As a result, F1F2 symbols may be used. They have much better autocorrelation property. As for the P symbols for narrowband, they may still be used for channel estimation and initial phase reference estimation, same as was the case for wideband. The symbols M1 or M2 proposed for FCC, ARIB and CENELEC standards are also used for narrowband for the same purposes (frame synchronization and mode detection).

FIG. 4 is a diagram illustrating a symbol duration for data symbol for CENELC B and C according to one embodiment. Again, the same approach is used for PHY frame in ROBO mode that is the P and M symbol are exchanged.

ACK/NACK Signal

FIG. 5 is a diagram illustrating ACK signal for FCC, ARIB and CENELEC A according to one embodiment. This signal may be used when an acknowledgement is required to confirm whether the data is correctly received (ACK) or it is erroneous (NACK). The same waveform used in preamble with modified M symbol may be used as an ACK signal. The P with 90 degrees shift (M=jP) and P with 180 degrees shift (M=−P) may already reserved for normal mode and ROBO mode respectively. The P with 270 degrees shift (M=−jP) may be proposed to be used for ACK signaling.

This may simplifies the system, as only one waveform need to be stored in the transmitter and same detection circuit in the receiver as used for preamble detection, is used for ACK signal detection as well. If no signal is received during the specified period, it is interpreted as a NACK signal.

FIG. 6 is a diagram illustrating ACK signal for CENELEC B, C, and BC according to one embodiment. Again the same symbols as used for the preamble for the purpose of synchronization, may also be used for the ACK signal. During the time period that a device is waiting for an acknowledgement, the reception of this signal may be an indication that the data may have been delivered with no error. If the time expires and the ACK signal has not been received, it may be an indication that the data may have been lost or delivered in errors.

FIG. 7 is a diagram illustrating a base-band transmitter 700 according to one embodiment. The base-band transmitter 700 includes a Forward Error Correction (FEC) encoding unit 710, a modulator 720, a power spectral shaping (PSD) module 730, a switch 740, an output formatter 750, and a switch 760.

The base-band transmitter 700 may receive its input bits in one packet from the Media Access (MAC) Layer. The FEC encoding unit 710 may include a number of FEC encoders. Each FEC encoder may add parity bits to the data and the packet grows as it goes through various blocks in FEC encoding unit 710. At the end of the FEC encoding unit 710, the final packet may be broken down into small packet so that each small packet may be fitted into one OFDM symbol. The size of one small packet depends on the number of carriers used in each OFDM symbol. For example, in FCC band, the packet size becomes equal to 100 bits. In order to understand the size of data as well as signal dimensions at each various points in the transmitter baseband, the calculation method may be described in the following.

Packet Size Calculation:

The total number of bits carried by a PHY frame may be obtained by: N _(F) =N _(G) =Ncarr×Ns

The N_(F) and N_(G) may represent the size of packet (signal) at nodes (F) and (G), respectively. Where Ncarr is the number of carriers in each OFDM symbol and Ns is the number of symbols per PHY frame. Note that the Interleaver does not change the size of packet. The number of bits at point (E) may be given by: N _(E) =N _(F) ×R

The value R may be one for Normal mode and ¼ for ROBO Mode. In order to find M, the number of zeros may need to be padded at the output of convolutional encoder; first we need to calculate the maximum number of RS bytes. The maximum number of RS bytes (MaxRSbytes) at the output of RS encoder may be obtained by the following equation: MaxRSbytes=floor((N _(E)×CCRate−CCZeroTail)/8)

Where CCRate and CCZeroTail are the convolutional code rate (½) and the number of zeros to be added to the input of convolutional encoder (to terminate the states to zero state), respectively. And “8” refers to the length of each RS word that is one byte.

Therefore, the value of M may be obtained by: M=N _(E)−((MaxRSbytes×8)+6)×2

Table 6 shows the number of zeroes padded after convolutional encoder for various bands.

TABLE 6 Number of zeroes padded after convolutional encoder ROBO Normal (Bits) (bits) FCC  M = 12 M = 4 ARIB M = 6  M = 12 CELENEC A  M = 12 M = 4 CELENEC B M = 4 M = 4 CELENEC C M = 4 M = 4 CELENEC B, C M = 4 M = 4

The number of bits at point (D), (C) and (B) now may be calculated by: N _(D) =N _(E) −M, N _(C) =N _(D)/2, N _(B) =N _(C)−6

Finally, considering the fact the number of parity bytes in RS code may be equal to 8, the packet size delivered by MAC to the physical layer may be given by: N _(A)=(N _(B)/8−8)×8

Table 7 summarizes the input packet to the physical layer for various band and both normal and ROBO modes. It should be noted that CENELEC B and CENELEC C ROBO may not be able to have long header format (48-bit addressing) and RS parity of 16 Bytes at the same time because of the size of the packet limitations.

TABLE 7 Packet size delivered by MAC layer to PHY layer ROBO Normal (bits) (bits) FCC 424 1928 ARIB 392 1784 CELENEC A 304 1448 CELENEC B 168 888 CELENEC C 168 888 CELENEC B, C 288 1368

The packet size at various nodes in the FEC encoding unit 710 for each band (CENELEC (A, B, BC)/FCC/ARIB) may be calculated and summarized in Tables 8A, 8B, 8C, 8D, 8E, and 8F. The nodes A, B, C, D, E, and F are shown in FIG. 8.

TABLE 8A Packet Size at various node of FEC encoder for FCC band FEC Node Normal Mode ROBO Mode A 1928 424 B 1992 428 C 1998 494 D 3996 988 E 4000 1000 F 4000 4000

TABLE 8B Packet Size at various node of FEC encoder for ARIB band FEC Node Normal Mode ROBO Mode A 1784 392 B 1848 456 C 1854 462 D 3708 924 E 3720 930 F 3720 3720

TABLE 8C Packet Size at various nodes of FEC encoder for CENELEC A band FEC Node Normal Mode ROBO Mode A 1448 304 B 1512 368 C 1518 374 D 3036 748 E 3040 760 F 3040 3040

TABLE 8D Packet Size at various node of FEC encoder for CENELEC B band FEC Node Normal Mode ROBO Mode A 888 168 B 952 232 C 958 238 D 1916 476 E 1920 480 F 1920 1920

TABLE 8E Packet Size at various node of FEC encoder for CENELEC C band FEC Node Normal Mode ROBO Mode A 888 168 B 952 232 C 958 238 D 1916 476 E 1920 480 F 1920 1920

TABLE 8F Packet Size at various nodes of FEC encoder for CENELEC BC band FEC Node Normal Mode ROBO Mode A 1368 288 B 1432 352 C 1438 358 D 2876 716 E 2880 720 F 2880 2880

The preamble for these band are composed of 6 of positive (P) and 1½ symbols of Negative(M) symbols. Each symbol contains 256 samples and pre-stored and is transmitted prior to data symbols. The M symbols are sing reversed of P symbols and are used for frame synchronization. The P symbols are used for synchronization, channel estimation and initial carrier phase reference estimation. FIG. 8 is a diagram illustrating the FEC encoding unit 710 according to one embodiment. The FEC encoding unit 710 includes a data scrambler 810, a Reed-Solomon (RS) encoder 820, a zero padding 830, a convolutional encoder 840, a zero padding 850, a ROBO encoder 860, a switch 870, an interleaver 880, and an un-buffer 890. It is noted that the FEC encoding unit 710 may include more or less than the above elements. In addition, any one of the above elements may be implemented by hardware, software, firmware, or any combination of hardware, software, and firmware.

The FEC encoders may include Reed Solomon encoder 820 followed by convolutional encoder 840. In ROBO mode, an extra encoder namely Repetition Code (RC) or ROBO encoder 860 may be used after the convolutional encoder 840 that repeats the bits at the output of convolutional encoder 840 four times

The data scrambler 810 may help give the data a random distribution. FIG. 9A is a diagram illustrating the data scrambler 810 according to one embodiment. The data stream may be XOR-ed with a repeating pseudo random number (PN) sequence using the following generator polynomial: S(x)=x⁷+x⁴+1. The bits in the scrambler are initialized to all ones at the start of processing each PHY frame.

The RS encoder 820 encodes data from the scrambler 810. The RS encoder 820 may be may be created by shortening RS (255,247, t=4) and (255,239, t=8) code. The “RS symbol word length” (i.e., the size of the data words used in the Reed-Solomon block) may be fixed at 8 bits. The value of t (number of word errors that can be corrected) may be either 4 or 8 for different standards. For CENELEC B and C ROBO the RS parity of 8 Bytes (corresponding to t=4) should be used. The number of parity words in a RS-block is thus 2t words. The number of non-parity data words (bytes) in Reed-Solomon encoder 820 may be provided in Table 3. The first bit in time from the data scrambler 810 may become the most significant bit of that symbol. Each RS encoder input block (consisting of 247 symbols) is conceptually formed by one or more fill symbols (“00000000”) followed by the message symbols. Output of the RS encoder (with fill symbols discarded) may proceed in time from first message symbol to last message symbol followed by parity symbols, with each symbol shifted out most significant bit first.

Code Generator Polynomial g (x)=(x−α¹) (x−α²) (x−α³) . . . (x−α⁸)

Field Generator Polynomial: p (x)=x⁸+x⁴+x³+x²+1 (435 octal)

TABLE 9 RS encoder input/output packet size Normal Mode ROBO Mode N_(A)/N_(B (Bytes)) N_(A)/N_(B (Bytes)) FCC 241/249 53/61 ARIB 223/231 49/57 CENELEC A 181/189 38/46 CENELEC BC 171/179 36/44 CENELEC B 111/119 21/29 CENELEC C 111/119 21/29

The representation of α⁰ is “00000001”, where the left most bit of this RS symbol is the MSB and is first in time from the scrambler 810 and is the first in time out of the RS encoder 820. The packet size (in Bytes) at the input and output of RS encoder 820 (N_(A) and N_(B)) may be given in Table 9.

The zero padding 830 may pad six zeroes after the RS encoder 820.

FIG. 9B is a diagram illustrating the convolutional encoder 840 according to one embodiment. The convolutional encoder 840 may encode the bit stream at the output of the Reed-Solomon encoder 820 with a standard rate=½, K=7. The tap connections are defined as x=0b1111001 and y=0b1011011, as shown in FIG. 9B.

When the last bit of data to the convolutional encoder 840 may have been received, the convolutional encoder 840 may insert six tail bits, which may be required to return the convolutional encoder 840 to the “zero state”. This may improve the error probability of the convolutional decoder, which relies on future bits when decoding. The tail bits may be defined as six zeros. The number of bits at the input and the output of convolutional encoder may be given in Table 10.

TABLE 10 Convolutional encoder input/output packet sizes Normal Mode ROBO Mode N_(A)/N_(B) (bits) N_(A)/N_(B) (bits) FCC 1998/3996 494/988 ARIB 1854/3708 462/924 CENELEC A 1518/3036 374/748 CENELEC BC 1438/2876 358/716 CENELEC B  958/1916 238/476 CENELEC C  958/1916 238/476

The zero padding 850 may pad M zeroes after the convolutional encoder 840. M is given in Table 6.

The ROBO encoder 860 repeats the resulting packet after adding M number of zeros to the packet four times in ROBO mode. The ROBO encoder 860 may be only activated in ROBO mode. The repeat code may be implemented inside the interleaver 880. The switch 870 selects whether to bypass the ROBO encoder 860 or uses the output of the ROBO encoder 860 in ROBO mode.

The interleaver 880 interleaves the data packet selected from the switch 870. It may be used for both normal mode and ROBO mode. The interleaver 880 may use a linear block interleaver and may achieve the same performance of a random interleaver using a simpler architecture with less computation.

The un-buffer 890 breaks down the final packet into small packet so that each small packet may be fitted into one OFDM symbol, as described earlier.

FIG. 10 is a diagram illustrating the modulator 720 according to one embodiment. The modulator 720 includes a DBPSK modulator 1010, a zero padding 1020, an inverse Fast Fourier Transform (IFFT) 1030, and a cyclic prefix (CP) extension 1040. It is noted that the modulator 720 may include more or less than the above elements. In addition, any one of the above elements may be implemented by hardware, software, firmware, or any combination of hardware, software, and firmware.

FIG. 11A is a diagram illustrating the DBPSK modulator 1010 according to one embodiment. The DBPSK modulator 1010 includes a mapper 1110 and a differential modulator 1120.

The mapper 1110 map data bits for differential modulation. Each phase vector may use its predecessor (same carrier, previous symbol) as phase reference. The mapping function for DBPSK may be given in Table 11.

TABLE 11 DBPSK Encoding Table of Kth Sub carrier Input Bit Output Phase 0 Ψ_(k) 1 Ψ_(k) + π

The initial phase for the first symbol are the carrier phases of the preamble symbol and are provided in Table 12. Each value in Table 12 may be a multiple integer of π/8 and may be quantized by 4 bits. The preamble phase reference index in Table 12 may start from 1 and it may refer to the first carrier in the corresponding band as given in Table 13. Note that the carrier index may be numbered from 0 to 127. This may be been illustrated in FIG. 11B.

TABLE 12 Preamble Phase Vector Definition FCC ARIB CNLC A CNLC B CNLC C CNLC BC FCC ARIB FCC ARIB FCC ARIB c φ_(c) φ_(c) φ_(c) φ_(c) φ_(c) φ_(c) c φ_(c) φ_(c) c φ_(c) φ_(c) c φ_(c) φ_(c) 1 14 14 14 X X X 26 8 4 51 11 12 76 9 8 2 14 14 13 X X X 27 3 15 52 3 3 77 12 11 3 13 13 11 X X X 28 15 10 53 10 10 78 15 13 4 13 12 9 X X 29 10 5 54 1 1 79 3 0 5 12 12 6 X X 30 5 0 55 9 7 80 6 2 6 11 11 2 X X 31 0 11 56 15 14 81 9 4 7 10 10 12 X 31 11 5 57 7 4 82 12 6 8 9 8 6 X 33 6 0 58 13 10 83 14 7 9 8 7 14 X 34 0 10 59 4 0 84 0 8 10 6 6 6 35 11 4 60 10 6 85 3 10 11 5 4 12 36 5 14 61 0 11 86 5 10 12 3 2 2 37 15 7 62 6 0 87 7 11 13 1 0 7 38 9 1 63 12 5 88 9 12 14 14 13 10 39 3 10 64 1 10 89 10 13 15 12 11 13 40 12 3 65 7 15 90 11 13 16 9 8 15 41 6 12 66 12 4 91 12 14 17 7 5 0 42 15 5 67 1 8 92 13 14 18 4 2 1 43 8 14 68 7 12 93 14 14 19 1 15 1 44 1 6 69 11 0 94 15 20 14 11 45 10 14 70 0 4 95 0 21 10 8 46 3 7 71 5 8 96 0 22 7 4 47 11 14 72 9 11 97 1 23 4 0 48 3 6 73 13 15 98 1 24 0 12 49 11 14 74 1 2 99 1 25 11 8 50 3 5 75 5 5 100 2

TABLE 13 First and Last Carrier Indexes for each band C_(n1) C_(n2) FCC 3 102 ARIB 3 95 CELENEC-A 2 20 CELENEC-B 21 26 CELENEC-C 27 29 CELENEC-BC 21 29

FIG. 11B is a diagram illustrating the carrier index numbers according to one embodiment.

The IFFT 1030 may take the 256-point IFFT of the input vector and may generate the main 256 time domain OFDM words preceded by N_CP words of cyclic prefix. In other words, the last N_CP samples at the output of the IFFT 1030 may be taken and placed in front of symbol. The useful output may be the real part of the IFFT coefficients. FIG. 11C is a diagram illustrating the input/output configuration according to one embodiment. The first carrier C_(n1) and the last carrier index C_(n2) associated with each band may be given in Table 13.

FIG. 12 is a diagram illustrating the PSD shaping module 730 according to one embodiment. The PSD shaping module 730 includes a raised cosine shaping 1210, an overlapping 1220, and a pre-emphasis filter 1230.

FIG. 13A is a diagram illustrating a raised cosine function according to one embodiment. FIG. 13B is a diagram illustrating a overlapping and add operation according to one embodiment.

In order to reduce the out of band emission and to reduce the spectral side lobe, a window function may be applied. In one embodiment, the Raised Cosine shaping 1210 may be applied to all the data symbols. Then the tails and heads of successive symbols may be overlapped and added together by the overlapping 1220. This process is described below. Each side of a symbol may be first shaped by the raised cosine function as shown in FIG. 13A.

The windowing function at each 8-sample boundary may be a Raised Cosine function and its values are given in Table 14. The window function may have a value equal to one at other samples. Then the 8 tail and 8 head shaped samples of the symbol from each side of symbol may be overlapped with the tail and head samples of adjacent symbols as shown in FIG. 13B. In other words, In order to construct the n_(th) symbol, firstly its 8 head samples may be overlapped with the 8 tail samples of the (n−1)_(th) symbol and its 8 tail samples may be overlapped with the 8 head samples of the (n+1)_(th) symbol. Finally, the corresponding overlapped parts may be added together. Note that the head of the first symbol is overlapped with the tail of preamble. And the tail of last symbol may be sent out with no overlapping applied.

TABLE 14 The Raised Cosine Samples Head samples Tail samples 1 0 0.9619 2 0.0381 0.8536 3 0.1464 0.6913 4 0.3087 0.5000 5 0.5000 0.3087 6 0.6913 0.1464 7 0.8536 0.0381 8 0.9619 0

FIG. 14 is a diagram illustrating a preamble signal according to one embodiment.

Memory locations may need to be allocated in the baseband to store the preamble samples. The preamble samples may be prepared in advance and download into the baseband memory during initialization period by the processor that implements the MAC layer. Each sample of preamble symbol may have an 8-bit length. The preamble signal that may be added to the beginning of each PHY frame may be shown in FIG. 14. It may include 8 symbols of type P and 1.5 symbols of type M. The total number of samples may be equal to 2432 samples. The first and the last 8 samples may be shaped according to Raised Cosine window. Note that the last 8 samples may be overlapped by the first 8 samples of the first data symbol. In practice we only need to store 256 sample of symbol P, 256 samples of symbol M, the first and the last 8 samples. Note that the symbol M may be different in Normal mode from that in the ROBO mode. In the ROBO mode, symbol M may be signed reversed of the P symbol, so there may be no extra storage required to store another symbol M for ROBO mode. In normal mode, the M symbol may have 90° phase shift from the P symbol.

FIG. 15 is a diagram illustrating the pre-emphasis filter 1230 according to one embodiment.

Time-Domain Pre-Emphasis Filter:

A time-domain pre-emphasis filter 1230 may be a linear equalization method where the transmit signal spectrum may be shaped to compensate for amplitude distortion. The purpose of this filter may be to provide frequency shaping to the transmit signal in order to compensate for attenuation introduced to the signal as it goes through the power line.

The pre-emphasis filter 1230 may be a first order recursive filter with transfer function of H(z)=0.5*[(Gamma+Beta*z^−1)/(1−R*z^−1)]. It may be specified with below deference equation: y(n)=0.5*[Gamma*x(n)+Beta*x(n−1)+R*y(n−1)]

As shown, the pre-emphasis filter 1230 may have one zero and one pole. In this implementation Gamma, Beta, and R may be programmable and may be assigned 16-bit registers. The pre-emphasis filter 1230 may be the last block in the transmit path right before the output formatter 750. The pre-emphasis filter may have the following register requirements: an enable/disable bit to enable/bypass the pre-emphasis filter, a Gamma register (signed 16 bits): parameter to control the shape of the pre-emphasis filter, a Beta register (signed 16 bits): parameter to control the shape of the pre-emphasis filter, and an R register (signed 16 bits): parameter to control the shape of the pre-emphasis filter.

Frequency Domain Pre-Emphasis Filter:

FIG. 16 is a diagram illustrating the pre-emphasis filter according to one embodiment. The purpose of this block may be to provide frequency shaping to the transmit signal in order to compensate for attenuation introduced to the signal as it goes through the power line.

The frequency-domain pre-emphasis filter may include of a multiplier that may multiply the complex frequency domain samples of an OFDM symbol with 128 real filter coefficients, then do four right shifts at the output. The filter coefficients may be 5 bits representing unsigned values from 0 h to 10 h. The filter coefficients may not be allowed to have values larger than 10 h. The filter may multiply the first 128 frequency-domain complex samples of an OFDM symbol with the 128 real coefficients of the filter. The rest of the 128 frequency-domain samples of the OFDM symbol may be usually set to zero and may not be multiplied by the filter coefficients. As the block diagram below shows, the input complex samples may be 8 bits each while the filter coefficients may be 5 unsigned bits each. Since the maximum allowed value of any filter coefficients may be 10 h, the output of the multiplication may be 12 bits (not 13 bits). The output may then be right shifted by 4 to get a final output of 8 bits that may be used as input to the IFFT.

The filter coefficient values may vary from 0 to 16, and since we do 4 right shifts at the output, it follows that the filter may provide the following attenuation for any of the 128 carriers:

Scaling factor attenuation in dB 16/16  0 dB 15/16  −0.53 dB 14/16  −1.16 dB 13/16  −1.8 dB 12/16  −2.5 dB 11/16  −3.25 dB 10/16  −4 dB 9/16 −5 dB 8/16 −6 dB 7/16 −7.2 dB 6/16 −8.5 dB 5/16 −10.1 dB 4/16 −12 dB 3/16 −14.5 dB 2/16 −18 dB 1/16 −24 dB 0/16 −infinite

The following registers may be needed to control the frequency-domain pre-emphasis filter: Enable/Disable bit: Allows for enabling/disabling the filter.

Transmitter (TX) P and D Scaler:

In order to control the transmitted power level of P and M in relation to power level of data two scalers may be implemented in the transmitter: a Data scaler to scale the data, and a P/M scaler to control the levels of the P & M that we are now generating from the frequency domain using the IFFT. Both scalers may be described below. On the receiver path, no scaling may be needed.

FIG. 17A is a diagram illustrating a data scaler on the transmitter data path according to one embodiment. FIG. 17B is a diagram illustrating a P and M scaler on the transmitter data path according to one embodiment. FIG. 17C is a diagram illustrating a scaler for frequency-domain P and M signals according to one embodiment. FIGS. 17A and 17B are provided to show how the 4-bit sync reference may be generated and scaled. The P/M scaler is used to scale IFFT output of frequency-domain P and M so that their levels may be as close as possible to original time-domain P & M. Once that is accomplished, the data scaler is used to achieve the desired P/Data RMS ratio. In what follows, the P/M scaler is described first, followed by the data scaler, which may have an identical architecture.

FIG. 17C shows how the IFFT output of frequency-domain P and M may be scaled so that their levels may be as close as possible to original time-domain P & M. This block may be called the “P/M Scaler”. The table lists the values for P_scale_factor and P_shift_factor registers for the different wideband and narrowband standards.

The data scaler may have identical block to the P/M scaler except that P_scale_factor is renamed to Data_scale_factor, and P_shift_factor is renamed to Data_shift_factor, where both may remain 8 bits each. The table shows the default values for the data scalers for the different standards.

FIG. 18 is a diagram illustrating a receiver 1800 according to one embodiment. The receiver 1800 includes a data formatter 1810, a direct current (DC) blocker 1815, an analog automatic gain control (AGC) processor 1820, a processing unit 1830, a digital AGC processor 1840, a demodulator 1850, a symbol synchronizer 1852, a frame synchronizer 1854, a preamble FFT coefficient buffer 1860, a mode detector 1870, and a FEC decoding unit 1880. It is noted that the receiver 1880 may include more or less than the above elements. In addition, any one of the above elements may be implemented by hardware, software, firmware, or any combination of hardware, software, and firmware.

FIG. 19 is a diagram illustrating the demodulator 1850 according to one embodiment. The demodulator 1850 includes a cyclic prefix (CP) remover 1910, a FFT processor 1920, and a DBPSK demodulator 1930.

FIG. 20 is a diagram illustrating the FEC decoding unit 1880 according to one embodiment. The FEC decoding unit 1880 includes a buffer 2010, a de-interleaver 2020, a ROBO combiner 2030, a zero remover 2040, a Viterbi decoder 2050, a RS decoder 2060, and a descrambler 2070. It is noted that the FEC decoding unit 1880 may include more or less than the above elements. In addition, any one of the above elements may be implemented by hardware, software, firmware, or any combination of hardware, software, and firmware.

On the receiver side, the PHY layer may receive its input samples from the power line and may hand the demodulated data bits over to the MAC layer. The processing unit 1830 may include a first infinite impulse response (IIR) filter 1832, a second IIR filter 1834, a jammer canceller 1836, and a root mean square (RMS) module 1838. The jammer canceller 1836 removes interference or a jamming signal in the input signal. The symbol synchronizer 1852 and the frame synchronizer 1854 may be used for preamble (ACK signal) detection, symbol and frame synchronization. The frame synchronizer 1854 and the preamble FFT coefficient buffer 1860 may be used to perform the initial preamble phase and the channel estimation, respectively.

The synchronizers 1852 and 1854 and the jammer canceller 1836 may be ON when the system is in the “Receive” mode. If the jammer or interfering signal may be present in the channel and detected, a switch may be set so that the signal may be taken from the output of the jammer canceller 1836. The jammer detector in the jammer canceller 1836 may do this automatically. The mode detector 1870 detects the mode of operation and sets an ACK flag 1872 or a ROBO flag 1874 as appropriate.

Two different synchronizer circuits, one for FCC, ARIB and CENELEC bands (Wideband OFDM) and another for CENELEC B, C and BC (Narrow band OFDM), may be used for different bands. The tasks for synchronizers may be the detection of preamble and obtaining the start of preamble symbol (symbol synchronizer) and the start of data symbol (frame synchronizer). As soon as the start of data symbol may be found, a switch may be moved to place the CP remover in the demodulator 1850 (FIG. 19) in the signal path. At the same time a timer 1865 may be enabled to generate the Physical Carrier Sense (PCS) signal. This signal may be high for the entire frame period. It may be at the end of PCS signal that the ACK flag 1872 and the ROBO flag 1874 are reset. Note that same waveforms may be used for ACK signaling and therefore as soon as the preamble is detected the ACK flag 1872 may be set. The value of this flag may be read by the MAC software and may be reset at the end of PCS signal. Note that the frame synchronizer 1854 may also detect if the PHY frame may be in ROBO mode or in Normal mode accordingly set/reset the ROBO flag 1874.

Once the symbol synchronizer identifies the start of preamble symbols, the initial channel estimator may be activated. At this time a switch may be set since there may be no cyclic prefix extension for preamble symbols. This block may measure the reference phase from the preamble. It may also measure the channel quality at each frequency bin. The channel estimator may also estimate the SNR for each carrier.

The ROBO flag 1874 may select the position of a switch in the FEC decoding unit 1880. Depending on the preamble waveform, the frame synchronizer 1854 may identify if the frame is in ROBO mode or in Normal Mode and the switch in the FEC decoding unit 1880 is set accordingly.

FIG. 21 is a diagram illustrating timings associated with events in the receiver according to one embodiment.

The data formatter 1810 may take the data bits from the analog-to-digital converter (ADC) and may perform tasks including, scaling, and mapping to convenient signed value representation. The DC blocker 1815 may be used to remove the DC component of incoming data. Since A/D converters and analog front-end circuitry may not be expected to be totally DC free, this filter may remove the DC residual. FIG. 22 is a diagram illustrating the DC blocker 1815 according to one embodiment. The DC blocker 1815 may be a first order recursive filter with transfer function of H(z)=1−z⁻¹/1−Az⁻¹. It may be specified with the deference equation y(n)=x(n)−x(n−1)+A y(n−1). DC blocker may have a zero at DC (z=1) and a pole near DC at z=A. In order to have the pole and zero cancel each other A may be selected as close as possible to unit circle. In one embodiment, A=0.995*2¹⁵=32604. The DC blocker 1815 may be the first block in receiver path before jammer canceller 1836. An enable/disable register may be allocated for the DC blocker 1815.

FIG. 23 is a diagram illustrating the FFT 1920 according to one embodiment. The same structure as used for the IFFT in the transmitter is used for FFT as well.

FIG. 24 is a diagram illustrating the DBPSK demodulator 1930 according to one embodiment. The phase difference between carriers over successive symbols may be estimated after the FFT of the current symbol may be multiplied by the conjugate values of the FFT of the previous symbol. The size of the signal at each node in FIG. 4.15 may be equal to the number of carriers (Ncarr). The real value of the signal at the output of multiplier may be taken and quantized appropriately by soft detection block. Each bit (carried by each carrier) may be represented by an integer number. The value of this number may depend on the reliability of the bit. The length of this integer number may be provided in fixed-point implementation.

The bit de-interleaver 2020 may reverse the mappings described in the transmitter section.

FIG. 25 is a diagram illustrating the ROBO combiner/decoder 2030 according to one embodiment. In ROBO mode, the encoded data may be extended 4 times by parity bits. For the repeat code, the soft values for each demodulated carrier are obtained. Then all the four values associated with one data bit may be averaged prior to hard decoding. The errors at the output of Viterbi decoder tend to occur in a burst fashion. To correct these burst errors a RS code may be concatenated with convolutional code.

FIG. 26 is a diagram illustrating the RS decoder 2060 according to one embodiment.

The de-scrambler 2070 may reverse the scrambling action, done on the source information bits in the transmitter.

Soft Repetition Code Combiner Using Channel State Information:

Repetition coding may be a simple yet effective coding scheme for noisy channels. The basic idea behind repetition coding may be that noise may be modeled as a zero mean Gaussian variable. The soft repetition code combiner may provide a means to boost the performance of the system by incorporating the channel state information measured over several symbols in the repetition decoder. The soft repetition code combiner may present a way to find the channel state information per tone and may combine that with the repetition combiner to propose a modified technique to generate soft or hard bits. The technique may increase the coding gain hence reliability of the system in robust mode; allow coding gain per tone to be weighted based on tone quality such that tones with low SNR, contribute less weight to the decoding decision compared to tones with high SNR; and increase the range of the system by providing more coding gain. This approach may be used in power line communication as well as modem designs.

In order to utilize the coding gain from repetition code, two soft repetition combiners may be proposed (vs. hard combiner where each soft value is mapped to 0 or 1 and a majority logic decoder is then used to make the decoding decision). In the first approach, the technique decodes a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. In the second approach, the technique decodes a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.

FIG. 27 is a diagram illustrating the soft ROBO combiner/decoder 2030 according to one embodiment. The ROBO combiner/decoder 2030 includes a slicer 2710, a de-interleaver 2720, a channel state estimator 2730, a quantizer 2740, a combiner 2750, and a comparator 2760. It is noted that the soft ROBO combiner/decoder 2030 may include more or less than the above elements. In addition, any one of the above elements may be implemented by hardware, software, firmware, or any combination of hardware, software, and firmware.

The slicer 2710 slices output of the demodulator 1850. In one embodiment, the slicer 2710 slices the output to one-bit symbols. The sliced output represents symbols of received signal from a power line. The de-interleaver 2720 de-interleaves the symbols. The channel state estimator 2730 generates a tone value representing channel information. The quantizer 2740 quantizes the tone value. The combiner 2750 combines, or adds, the de-interleaved symbols weighed by the quantized tone value. The comparator 2760 compares the combined de-interleaved symbols with a threshold to generate a decoding decision. In one embodiment, the weight has a 3-bit length and for each carrier is separately calculated based on the tone values used for channel estimation. This approach allows coding gain per tone to be weighted based on tone quality such that tones with low signal-to-noise ratio (SNR) contribute less weight to the decoding decision compared to tones with high SNR.

The channel state estimator 2730 calculates the tone values. Channel information is obtained from constellation points at the output of the differential demodulator. Individual sub channels are assessed by counting the number of demodulated constellation points, which fall within a given angle of the expected constellation point. Channel information is gathered over one data frame. The channel estimate collected from each frame may be passed to the channel control software where it may be accumulated over time.

FIG. 28 is a diagram illustrating the channel state estimator 2730 using tone value according to one embodiment. The channel state estimator 2730 includes a counter 2810, a total count generator 2820, and a tone value generator 2830.

The counter 2810 counts a tone count representing a number of constellation points at outputs of the demodulator 1850 for a carrier. The total count generator 2820 generates a total count representing a quality measure of the carrier. The tone value generator 2830 generates the tone value using the total count. The tone value representing an accumulated measure of a carrier quality using previous channel information.

FIG. 29 is a diagram illustrating the four measurement regions over constellation plane according to one embodiment. The tangent of measurement angles is 1 over 4. The four measured channel estimates are named ToneCountR, ToneCountL, ToneCountU and ToneCountD. Overall (all four regions) measure of quality or ToneCount is calculated for each carrier using the following formula: ToneCount(n)=Scalar α×(ToneCountR(n)+ToneCount(n)+ToneCountU(n)+ToneCountD(n))

The scaler α, is to reduce round off noise in future calculations. The value of α may be selected according to particular implementations. In one embodiment, a is selected to be 128. Higher ToneCount value means a better quality for a specific carrier.

After calculating per carrier quality measures or ToneCounts based on the latest estimation report from hardware, an accumulated measure of carriers' quality is calculated using previously available channel information. This is called “ToneValue” or accumulated measure of quality for each carrier for a given ToneMap Index. The past estimate of the carriers' quality is blended with the new channel measurements or ToneCounts. The weight of the old measurements or ToneValues depends on the number of past channel observations and the time elapsed from the last received channel report. This time dependent variable is named TotalCount. The following shows how TotalCount and ToneValues are updated:

${TotalCount} = {{Totalcount} \times {\Lambda\left( \frac{t}{T} \right)}}$ ${{ToneValue}(n)} = \frac{{{TotalCount} \times {{ToneValue}(n)}} + {{ToneCount}(n)}}{{TotalCount} + {BlockSize}}$ TotalCount = TotalCount + BlockSize if  TotalCount > threshold, TotalCount = threshold

TotalCount is initially set to zero. It is also reduced to zero when the old measurement is “stale” or when elapsed time from last measurement report (t) is greater than T. A stale time of 30 seconds may be considered here. For any time elapsed less than T, TotalCount is proportionally reduced, lowering the weight of the old channel measurement. TotalCount is increased by the BlockSize of each new channel measurement report to a limited value of 160. This threshold limit is set by computer simulations and can be changed in software. In one embodiment, threshold is selected to be 160.

The total count generator 2820 resets the total count to zero when an elapsed time from a last measurement report is greater than a pre-determined time interval. It reduces the total count according to age of channel measurement and increases the total count by a block size up to a pre-determined threshold. The quantizer 2740 includes a mapper to translate the tone value into an N-bit weight corresponding to a carrier.

ROBO is the optimum mode if all scaled numbers are less than a predetermined limit. In one embodiment, this limit is 32. The reason for scaling is that, with an equal number of carriers, the data rate per carrier in Modes 2 and 3 are twice and three times that of Mode 1, respectively. Maximizing the data rate, the desired Mode of operation or DesiredMode and the corresponding ToneMap or DesiredToneMap is obtained. Notice that in Mode 0 (RPBO) all carriers are always used.

FIG. 30 is a diagram illustrating the tone value quantizer characteristics used to get soft values according to one embodiment. Soft values extracted from tone values are used in ROBO maximal ratio combiner and potentially in soft Viterbi decoder. Soft values are in fact 3-bit digitization of tone values as shown in FIG. 30. Tone values are positive integers with a maximum value of 128.

The second approach uses averaging. In this architecture, a 3-bit quantizer may replace the one-bit slicer after the demodulator. Moreover, the channel estimation may use the same quantized demodulator output instead of the tone value; however, averaging over 8 symbols is performed to mitigate noise effect. This technique multiplies the received data after demodulation by the corresponding channel estimates. In this structure, the data at the output of the multiplier in demodulator block are quantized to the size of the datapath. Quantizer controls the power consumption and silicon size of the integrated circuit.

In the proposed technique, more accurate estimate for the channel behavior for each carrier is obtained by averaging. It is seen that in order to obtain the channel response at each carrier frequency, the amplitude of each carrier is estimated by averaging over 8 subsequent carriers. As a result of these modifications, simulation results show that the proposed technique provide 1.5 dB improvement in AWGN channel and about 8 dB improvement in a typical selective channel environment as compared with the original method (using 1-bit demodulator value and 3-bit tone value using counters)

FIG. 31 is a diagram illustrating the ROBO combiner/decoder 2030 using averaging according to one embodiment. The ROBO combiner/decoder 2030 includes a first quantizer 3110, a second quantizer 3120, a channel estimator 3130, a multiplier 3140, a de-interleaver 3150, an averager 3160, and a slicer 3170.

The first quantizer 3110 generates the quantized output of the demodulator. The second quantizer 3120 generates input to the channel estimator 3130 corresponding to the carrier. The channel estimator 3130 provides a channel estimate. The multiplier 3140 multiplies a quantized output of the demodulator 1850 with the channel estimate to produce N symbols of a signal corresponding to a carrier. In one embodiment, N is a power of 2 (e.g., 8). The de-interleaver 3150 de-interleaves the N symbols. The averager 3160 averages the N de-interleaved symbols to generate a channel response at a carrier. The slicer 3170 slices the channel response to provide a decoding decision.

FIG. 32 is a diagram illustrating the averager 3160 according to one embodiment. The averager 3160 includes N−1 storage elements connected in cascade to store N−1 de-interleaved symbols; and an adder coupled to the (N−1) storage elements to add the N de-interleaved symbols including the N−1 stored de-interleaved symbols.

FIG. 33 is a diagram illustrating the performance on AWGN channel according to one embodiment. FIG. 34 is a diagram illustrating the frequency selective channel model used in simulations according to one embodiment. FIG. 35 is a diagram illustrating the performance in frequency selective fading according to one embodiment.

Elements of one embodiment may be implemented by hardware, firmware, software or any combination thereof. The term hardware generally refers to an element having a physical structure such as electronic, electromagnetic, optical, electro-optical, mechanical, electro-mechanical parts, etc. A hardware implementation may include analog or digital circuits, devices, processors, applications specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), or any electronic devices. The term software generally refers to a logical structure, a method, a procedure, a program, a routine, a process, an algorithm, a formula, a function, an expression, etc. The term firmware generally refers to a logical structure, a method, a procedure, a program, a routine, a process, an algorithm, a formula, a function, an expression, etc., that is implemented or embodied in a hardware structure (e.g., flash memory, ROM, EPROM). Examples of firmware may include microcode, writable control store, micro-programmed structure. When implemented in software or firmware, the elements of an embodiment are essentially the code segments to perform the necessary tasks. The software/firmware may include the actual code to carry out the operations described in one embodiment, or code that emulates or simulates the operations.

The program or code segments can be stored in a processor or machine accessible medium. The “processor readable or accessible medium” or “machine readable or accessible medium” may include any medium that may store, transmit, receive, or transfer information. Examples of the processor readable or machine accessible medium that may store include a storage medium, an electronic circuit, a semiconductor memory device, a read only memory (ROM), a flash memory, an erasable programmable ROM (EPROM), a floppy diskette, a compact disk (CD) ROM, an optical disk, a hard disk, etc. The machine accessible medium may be embodied in an article of manufacture. The machine accessible medium may include information or data that, when accessed by a machine, cause the machine to perform the operations or actions described above. The machine accessible medium may also include program code, instruction or instructions embedded therein. The program code may include machine readable code, instruction or instructions to perform the operations or actions described above. The term “information” or “data” here refers to any type of information that is encoded for machine-readable purposes. Therefore, it may include program, code, data, file, etc.

All or part of an embodiment may be implemented by various means depending on applications according to particular features, functions. These means may include hardware, software, or firmware, or any combination thereof. A hardware, software, or firmware element may have several modules coupled to one another. A hardware module is coupled to another module by mechanical, electrical, optical, electromagnetic or any physical connections. A software module is coupled to another module by a function, procedure, method, subprogram, or subroutine call, a jump, a link, a parameter, variable, and argument passing, a function return, etc. A software module is coupled to another module to receive variables, parameters, arguments, pointers, etc. and/or to generate or pass results, updated variables, pointers, etc. A firmware module is coupled to another module by any combination of hardware and software coupling methods above. A hardware, software, or firmware module may be coupled to any one of another hardware, software, or firmware module. A module may also be a software driver or interface to interact with the operating system running on the platform. A module may also be a hardware driver to configure, set up, initialize, send and receive data to and from a hardware device. An apparatus may include any combination of hardware, software, and firmware modules.

It will be appreciated that various of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. Various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims. 

What is claimed is:
 1. An apparatus comprising: a channel estimator to provide a channel estimate; a multiplier coupled to the channel estimator to multiply a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier, wherein N is an integer greater than one; a de-interleaver coupled to the multiplier to de-interleave the N symbols; and an averager coupled to the de-interleaver to average the N de-interleaved symbols to generate a channel response at the carrier.
 2. The apparatus of claim 1 further comprising: a first quantizer to generate the quantized output of the demodulator; and a second quantizer to generate input to the channel estimator corresponding to the carrier; and a slicer coupled to the averager to slice the channel response to provide a decoding decision.
 3. The apparatus of claim 1 wherein the averager comprises: N−1 storage elements connected in cascade to store N−1 de-interleaved symbols; and an adder coupled to the (N−1) storage elements to add the N de-interleaved symbols including the N−1 stored de-interleaved symbols.
 4. The apparatus of claim 1 wherein N is a power of two.
 5. The apparatus of claim 1 wherein the signal is received from a power line.
 6. The apparatus of claim 1 wherein the demodulator is compatible with Orthogonal Frequency Division Multiplexing (OFDM).
 7. A method comprising: providing a channel estimate; multiplying a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier, wherein N is an integer greater than one; de-interleaving the N symbols; and averaging the N de-interleaved symbols, the averaged N de-interleaved symbols representing a channel response at the carrier.
 8. The method of claim 7 further comprising: generating the quantized output of the demodulator; and generating input to the channel estimator corresponding to the carrier; and slicing the channel response to provide a decoding decision.
 9. The method of claim 7 wherein averaging comprises: storing N−1 de-interleaved symbols in N−1 storage elements connected in cascade; and adding the N de-interleaved symbols including the N−1 stored de-interleaved symbols.
 10. The method of claim 7 wherein N is a power of two.
 11. The method of claim 7 wherein the signal is received from a power line.
 12. The method of claim 7 wherein the demodulator is compatible with Orthogonal Frequency Division Multiplexing (OFDM).
 13. A system comprising: a demodulator to demodulate a signal received from a power line; and a decoder coupled to the demodulator to decode the demodulated signal, the decoder comprising: a channel estimator to provide a channel estimate, a multiplier coupled to the channel estimator to multiply a quantized output of the demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier, wherein N is an integer greater than one, a de-interleaver coupled to the multiplier to de-interleave the N symbols, and an averager coupled to the de-interleaver to average the N de-interleaved symbols to generate a channel response at the carrier. 